1. Field of the Invention
The present invention relates to a nonvolatile memory device, and particularly to a nonvolatile memory device having a plurality of memory cells arranged in a matrix, each memory cell including a variable resistor element for storage of data through changing its electrical resistance with the use of electrical stress.
2. Description of the Related Art
Flash memories are known as nonvolatile memory devices. Such flash memories have continuously been demanded for downsizing. For the purpose, the charge in the floating gate is declined to minimize the control of threshold voltage or the length of channels is decreased to minimize the withstanding pressure between source and drain. However, the downsizing along a plane of flash memories is now close to its limit.
Improved memories are then proposed where the miniaturization is shifted from along the plane to along a stack of layers (in the vertical direction). Such improved memories include, for example, FeRAM, MRAM, PRAM, and resistive RAM (RRAM: registered trademark of Sharp Corporation). RRAM among them is now focused as most favorable for minimizing the size along the stack of layers. RRAM is designed for modifying the resistance to electrically write data.
Some conventional RRAMs are known including U.S. Pat. No. 6,204,139, “Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)” by W. W. Zhung et al, IEDM in 2002, and “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses” by I. G. Bake et al, IEDM in 2004. In common, the fundamental structure of variable resistor elements in RRAM has a transition metal oxide sandwiched between the upper electrode and the lower electrode. Examples of transition metal oxide are PrxCa1-xMnO3, SmxCa1-xMnO3, TiO2, NiO, HfO2, and ZrO2.
In general, the memory cell array of RRAM may be implemented by a cross-point array (1R array) structure (as depicted in “A 512 kb Cross-Point Cell MRAM” by N. Sakimura et al, ISSCC, 16.1, in 2003). FIG. 10A is a perspective view showing an example of a part of a conventional 1R array circuit (referred to as a conventional device hereinafter). FIG. 10B is a cross sectional view of the conventional device taken along the vertical direction of FIG. 10A. In the drawings, the electrical insulators provided between memory cells are not illustrated.
The conventional device has a number of memory cells 110 arranged at the intersections between the parallelly extending bit lines 101 and the parallelly extending word lines 103 which are orthogonal to the bit lines 101. The memory cell 110 comprises a variable resistor element 102. Since the conventional device needs no switching element such as a transistor provided in each memory cell 110, its memory cell array can easily be constructed in a multi-layer structure where layers are deposited along the vertical direction. Accordingly, when its memory cell 110 has an N number of layers, the memory cell array can be as small as 4F2/N in the area (F being the minimum fabrication line width and N being the number of layers). This allows the area of a memory cell array in a nonvolatile memory device to be smaller.
The read action and the write action in the conventional device will be explained. FIGS. 11 to 13 are schematic views showing the memory cell array structure of a conventional device. A number of word lines WL0 to WLn extend along the columns while a number of bit lines BL0 to BLn extend along the rows. Each memory cell is arranged at the intersection between one of the word lines WL0 to WLn and one of the bit lines BL0 to BLn. In FIGS. 11 to 13, the variable resistor element at each intersection between the word line and the bit line is not illustrated. It is defined that a program action means that the variable resistor element in a memory cell shifts from the low resistance mode to the high resistance mode while the reset action means that the variable resistor element in the memory cell returns back from the high resistance mode to the low resistance mode.
The read action at the conventional device will first be explained. For reading data from the selected memory cell to be read, the action starts applying a read voltage (+Vread) to all the word lines, applying the read voltage (+Vread) to the unselected bit lines not connected to the selected memory cell, and applying 0 V to the selected bit line connected to the selected memory cell, as shown in FIG. 11 and Table 1. It is then judged from the measurement of a current in the word line whether the variable resistor element in each selected memory cell connected to the selected bit line is at the low resistance mode or the high resistance mode.
TABLE 1Selected memory cellUnselected memory cellWord line voltage+Vread+VreadBit line voltage0+VreadVoltage difference+Vread0
The program action at the conventional device will then be explained. For programming data in selected one of the memory cells as a target of writing, the action starts applying a program voltage (+Vpp) to the selected word line connected to the selected memory cell, applying a voltage (+Vpp/2) to the unselected word lines not connected to the selected memory cell, applying a voltage (+Vpp/2) to the unselected bit lines not connected to the selected memory cell, and applying 0 V to the selected bit line connected to the selected memory cell, as shown in FIG. 12 and Table 2. This allows the selected memory cell to be applied with the program voltage +Vpp. Simultaneously, the unselected memory cells A along the selected word line and the unselected memory cells B along the selected bit line are applied with a voltage +Vpp/2 as a disturb voltage. It is common that the program voltage Vpp is determined so as not to permit its disturb voltage performing program action at the memory cell.
TABLE 2SelectedUnselectedUnselectedUnselectedmemory cellmemory cell Amemory cell Bmemory cellWord line+Vpp+Vpp+Vpp/2+Vpp/2voltageBit line0+Vpp/20+Vpp/2voltageVoltage+Vpp+Vpp/2+Vpp/20difference
The reset action at the conventional device will then be explained. For resetting the memory cells to be selected as a target of resetting, the action starts applying a reset voltage (+Vpp) to the selected bit line connected to the selected memory cell, applying a voltage (+Vpp/2) to the unselected word lines not connected to the selected memory cell, applying a voltage (+Vpp/2) to the unselected bit lines not connected to the selected memory cell, and applying 0 V to the selected word line connected to the selected memory cell, as shown in FIG. 13 and Table 3. This allows a reset voltage −Vpp to be applied to the selected memory cell. Simultaneously, a disturb voltage of −Vpp/2 is applied to the unselected memory cells A along the selected word line and the unselected memory cells B along the selected bit line. It is common that the reset voltage Vpp is determined so as not to permit its disturb voltage performing reset action at the memory cell.
TABLE 3SelectedUnselectedUnselectedUnselectedmemory cellmemory cell Amemory cell Bmemory cellWord line00+Vpp/2+Vpp/2voltageBit line+Vpp+Vpp/2+Vpp+Vpp/2voltageVoltage−Vpp−Vpp/2−Vpp/20difference
In the program action at the conventional device, a voltage difference of +Vpp generated in the selected memory cell allows a current to flow into the selected memory cell. This causes Joule heat in the selected memory cell hence increasing the temperature of the variable resistor element in the selected memory cell. As the result, the variable resistor element is considered to shift from the low resistance mode to the high resistance mode.
However, the conventional device permits Joule heat generated in the selected memory cell 110 to conduct via the bit line 101 or the word line 103 to an adjacent unselected memory cell 111, as shown in FIG. 14. More particularly, as the bit line 101 and the word line 103 acts as a thermal diffusion path, the variable resistor element 102 in the unselected memory cell 111 will be increased in the temperature. In other words, the variable resistor element 102 in the unselected memory cell 111 will become highly variable in the resistance. Either the word line or the bit line is common to the memory cells adjacent to the selected memory cell and the selected memory cell. Since the disturb voltage is applied to the unselected memory cell 111, a change in the resistance in its variable resistance element will be encouraged by a combination of the disturbed voltage and Joule heat received from the adjacent selected memory cell thus resulting in a fault program action at the unselected memory cell 111.